The present disclosure generally relates to the field of electronics. More particularly, an embodiment Of the invention relates to transferring data between clock domains.
As integrated circuit fabrication technology improves, manufacturers are able to integrate additional functionality onto a single chip. With the increase in the number of these functionalities, the number of components on a single chip may also increase. To improve performance (e.g., by operating different components in parallel), some components of a chip may be in a different clock domain (e.g., operating at a different clock frequency) than other components of the same chip. When data is transferred between the different clock domains, data transfer latency may be increased, e.g., to ensure proper synchronization between the different clock domains. The data transfer latency may increase even further when the data traverses multiple clock domains.